View IDT5V996_925575.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM II PLUS
FEATURES:
* * * * * * * * * * * * * *
IDT5V996
3.3V operation 4 pairs of programmable skew outputs Low skew: 150ps same pair, 350ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: 25MHz to 225MHz Output frequency: 25MHz to 225MHz 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency) 3-level inputs for skew control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <150ps peak-to-peak Available in 144-pin BGA package
DESCRIPTION:
The IDT5V996 is a high fanout PLL based clock driver intended for high performance computing and data-communication applications. The IDT5V996 has eight programmable skew outputs organized in four banks of two. Skew is controlled by 3-level input signals that may be hard wired to appropriate HIGH-MID-LOW levels. The IDT5V996 provides up to 18 programmable levels of output skew, prescaling, and other features. Other features of IDT5V996 are synchronous output enable (G), TEST, and lock detect indicator (LOCK). When G is held low, all the outputs are synchronously enabled, however, if G is held high, all outputs except 3Q0 and 3Q1 are in the state designated by SE (HIGH or LOW). When TEST is held low, the chip operates in normal condition. When held high, the PLL is shut off and the chip functions as a buffer. The lock detect indicator asserts high when the phase lock loop has acquired lock. During acquisition, the indicator is in the low state. Once the PLL has reached the steady-state condition within a specified frequency range, LOCK is asserted high. The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT5V996 has LVTTL outputs with 12mA balanced drive outputs. The IDT5V996 is characterized for operation from -40C to +85C.
FUNCTIONAL BLOCK DIAGRAM
G Enable Logic
SE Skew Select
3 3 3
1Q0
1Q 1
1F2:0 TEST 2Q0 Skew Select
3 3 3
2Q1
REF PLL FB Skew Select
3 3 3
2F2:0
3Q 0
3Q1
LOCK
3F2:0
4Q0 Skew Select
3 3 3
4Q 1
4F2:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c 2001 Integrated Device Technology, Inc.
DECEMBER 2001
DSC 5855/4
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
A
VDDQ
VDDQ
VDDQ
GND
GND
LOCK
GND
GND
GND
VDDQ
VDDQ
VDDQ
A
B
VDDQ
VDDQ
VDDQ
GND
2Q1
2Q0
1Q1
1Q0
GND
VDDQ
VDDQ
VDDQ
B
C
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
C
D
VDDQ
VDDQ
VDD
GND
GND
GND
GND
GND
GND
VDD
2F2
2F1
D
E
VDDQ
G
VDD
GND
GND
GND
GND
GND
GND
VDD
2F0
1F2
E
F
TEST
REF
VDD
GND
GND
GND
GND
GND
GND
VDD
1F1
1F0
F
G
VDDQ
FB
VDD
GND
GND
GND
GND
GND
GND
VDD
4F1
4F0
G
H
VDDQ
SE
VDD
GND
GND
GND
GND
GND
GND
VDD
3F0
4F2
H
J
VDDQ
VDDQ
VDD
GND
GND
GND
GND
GND
GND
VDD
3F2
3F1
J
K
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
K
L M
VDDQ
VDDQ
VDDQ
GND
3Q1
3Q0
4Q1
4Q0
GND
VDDQ
VDDQ
VDDQ
L M
VDDQ
VDDQ
VDDQ
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
BGA TOP VIEW
2
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ, VDD VI
(2) (2)
CAPACITANCE(1,2)(TA = +25C, f = 1MHz, VIN = 0V)
Unit V V V mA mA mA C Parameter CIN Description Input Capacitance VI = VDDQ or GND
NOTES: 1. Unused inputs must be held high or low to prevent them from floating. 2. Capacitance applies to all inputs except nF2:0. This value is characterized but not production tested.
Description Supply Voltage Range Input Voltage Range Voltage range applied to any output in the high or low state Input Clamp Current Continuous Output Current Continuous Current Storage Temperature Range
Max -0.5 to +4.6 -0.5 to 4.6 -0.5 to VDDQ + 0.5 -50 50 100 -65 to +150
Min --
Typ. 8
Max. --
Unit pF
VO
IIK (VI < 0) IO (VO = 0 to VDDQ) VDDQ or GND TSTG
NOTES: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
PIN DESCRIPTION
Pin Name REF SE Type IN IN Description Reference Clock Input Selectable positive or negative edge control. When LOW / HIGH, the outputs are synchronized with the negative/positive edge of the reference clock. When outputs are synchronously stopped with the G pin, SE determines the level at which outputs stop. When SE is LOW/HIGH, outputs synchronously stop HIGH/LOW. Feedback Input Output gate for "true" nQ[1:0] outputs. When G is LOW, the "true" nQ[1:0] outputs are enabled. When G is HIGH, the "true" nQ[1:0] outputs are in the state designated by SE (HIGH or LOW) (except 3Q0 and 3Q1) - 3Q0 and 3Q1 may be used as the feedback signal to maintain phase lock. TEST = LOW means normal operation. TEST = HIGH means that the PLL is powered down and REF is routed to all the outputs. The skews selected with the nF[2:0] pins are still in effect. (The TEST pin is a TTL input.) nF[2:0] nQ[1:0] VDDQ VDD GND LOCK IN OUT PWR PWR PWR OUT 3-level inputs for selecting 1 of 18 skew taps or frequency functions Clock Output Pairs Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground Lock Detect. Asserted (HIGH) when the PLL is locked. The REF input must be oscillating.
FB G
IN IN
TEST
IN
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 278ps to 625ps (see Programmable Skew Range and Resolution Table). There are 16 skew configurations available for each output pair. These configurations are chosen by the nF2:0 control pins. In order to 3 minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF2:0 control pins.
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V996 gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
Comments Timing Unit Calculation (tU) VCO Frequency Range (FNOM)(1) Skew Adjustment Range(2) Max Adjustment: 4.375ns 157.5 43.75% Example 1, FNOM = 100MHz Example 2, FNOM = 167MHz Example 3, FNOM = 225MHz tU = 0.625ns tU = 0.374ns tU = 0.278ns ns Phase Degrees % of Cycle Time -- -- -- 1/(16 x FNOM) 100 to 225 MHz
NOTES: 1. The VCO frequency always appears at nQ1:0 outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be FNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the FB input. Using the nF[2:0] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals). 2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed -4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to all output pairs where 7tU skew adjustment is possible and at the lowest FNOM value.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS(1)
nF2 L L L L M M M M M M M M M H H H H H H nF1 L H H H L L L M M M H H H L L L M M M nF0 L L M H L M H L M H L M H L M H L M H Output Skew Disable(2) -7tU -6tU -5tU -4tU -3tU -2tU -1tU Zero Skew +1tU +2tU +3tU +4tU +5tU +6tU +7tU Inverted Divide by 2 Divide by 4
NOTES: 1. All unused/unnoted combinations are reserved. 2. When G is LOW, all output pairs are individually disabled to the level designated by SE. When SE is LOW/HIGH, output pairs disable HIGH/LOW.
4
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
RECOMMENDED OPERATING RANGE
Symbol VDD / VDDQ TA Description Power Supply Voltage Ambient Operating Temperature Min. 3 -40 Typ. 3.3 +25 Max. 3.6 +85 Unit V C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Level(1) Input MID Voltage Level Input Leakage Current (REF, FB Inputs Only) I3 VOH VOL 3-Level Input DC Current (nF2:0) Output HIGH Voltage Level Output LOW Voltage Level
(1) (1)
Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VCC or GND VCC = Max. VIN = VDD VIN = VDD/2 VIN = GND VDD = Min., IOH = -12mA VDD = Min., IOL = 12mA HIGH Level MID Level LOW Level
Min. 2 -- VDD-0.6 VDD/2-0.3 -- -5 -- -50 -200 2.4 --
Max. -- 0.8 -- VDD/2+0.3 0.6 +5 +200 +50 -- -- 0.4
Unit V V V V V A
Input LOW Voltage Level
A V V
NOTE: 1. These inputs are normally wired to VDDQ, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDDQ/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ Parameter Quiescent Power Supply Current Test Conditions(1) VDDQ = Max., REF = FB = SE = G = LOW, TEST = HIGH, All nF2:0 = All outputs floating IDDD ITOT Dynamic Power Supply Current per Output Total Power Supply Current VDDQ = Max., CL = 0pF VDDQ = 3.3V, FVCO = 100MHz, CL = 20pF VDDQ = 3.3V, FVCO = 167MHz, CL = 20pF VDDQ = 3.3V, FVCO = 225MHz, CL = 20pF
NOTES: 1. Measurements are for divide-by-1 outputs. 2. For nominal voltage and temperature. 3. This configuration is only specific for IDDQ measurements.
Typ.(2) --
Max. 30
Unit mA
HHM(3), 410 124 197 253 650 -- -- -- mA A/MHz
5
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol FNOM FREF tREF tU tSKEWPR tSK(0) tSK() tSK(INV) tSKEW1 tSKEW4 tDEV t tODCV tR tF tLOCK tJ VCO Frequency Range REF Clock Input Frequency REF Clock Duty Cycle Programmable Skew Time Unit Matched-Pair Skew (xQ0, xQ1)(1,2,3) Output Skew (Rise-Rise, Fall-Fall, Same Frequency and Phase) Multiple Frequency Skew(1,2) Inverting Skew Between Nominal and Inverted Output Skew (Rise-Fall, Inverted-Divided) Device-to-Device Skew(2,5) REF Input to FB Static Phase Offset (VTH = VDDQ/2) Output Duty Cycle Variation from 50%(1,7) Output Rise Time (0.8V to 2V) PLL Lock Time
(6) (1) (1,2) (1,2,4) (1,2)
Parameter
Min. 25 10 -- -- -- -- -- -- -- -250 -0.75 -- -- -- --
Typ. -- -- See Control Summary Table -- -- -- -- -- -- -- -- -- -- -- -- --
Max. 225 90 150 350 550 500 500 500 250 +250 +0.75 2.2 2.2 0.5 150
Unit MHz %
See PLL Programmable Skew Range and Resolution Table
ps
Output Skew (Rise-Fall, Divided-Divided)(1,2,4)
ns ns ns ms ps
Output Fall Time (2V to 0.8V)(1) Cycle-to-Cycle Output Jitter, Peak-to-Peak(1)
NOTES: 1. Measured at VTH = VDDQ/2, output load CL = 20pF. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted, and Divided (Divide-by-2 or Divide-by-4 mode). 5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.) 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD and VDDQ are stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7. tODCV is measured with nF[2:0] = MMM.
6
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
150
OUTPUT
150
20pF
AC Load
3V VTH =VDDQ/2 0V
Input Waveform
tR
tF
2 VTH 0.8
Output Waveform
150 REF nQn CL = 20pF IDT5V996 150
FB CF
3Q0
FBOUT
PCBTRACE
Static Phase Offset and Skew Calculations (2,3)
NOTES: 1. VTH = VDDQ/2. 2. CF = CL - CFBIN - CPCBTRACE; CFBIN 6pF 3. Calculations were done by adjusting the input slew rate to match with the output slew rate.
7
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM
tREF tRPW H
RE F
tRPW L
t()
tODCV
tO DC V
FB
tJ
Q
tSKEW P R tSK(O)
tSKEWPR tSK(O)
OTH ER Q
tSK(INV)
tSK(INV)
INV ER TE D Q
tSK() tSK() tSK()
REF D IVIDE D B Y 2
tSKEW1,4
tSKEW1,4
REF D IVIDE D B Y 4
NOTES: SE: Skew: tSKEWPR: tSK(0): tDEV: tODCV: tSK(): tSK(INV): tLOCK:
The AC Timing Diagram applies to SE=VDD. For SE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 to VDDQ/2. The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. The skew between outputs when they are selected for 0tU. The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW1 and tSKEW4 specifications. The skew between outputs of different frequencies. The skew between inverting and non-inverting outputs. The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
tR and tF are measured between 0.8V and 2V.
8
IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
I
-40C to +85C (Industrial)
BB
Plastic Ball Grid Array
5V996
3.3V Programm able Skew PLL Clock Driver TurboClock II Plus
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
9

▲Up To Search▲

Price & Availability of IDT5V996

	To Download IDT5V996 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .